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HYS 64/72V64220GU SDRAM-Modules
3.3 V 64M x 64/72-Bit, 512MByte SDRAM Modules 168-pin Unbuffered DIMM Modules
* 168-pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications using 256Mbit technology. * PC100-222, PC133-333 & PC133-222 versions * Two bank 64M x 64 and 64M x 72 organization * Optimized for byte-write non-parity and ECC applications * JEDEC standard Synchronous DRAMs (SDRAM) * Programmed Latencies: Product Speed -7 -7.5 -8 PC133 PC133 PC100 CL 2 3 2
tRCD tRP
* Single + 3.3 V ( 0.3 V) power supply * Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) * Auto Refresh (CBR) and Self Refresh * Decoupling capacitors mounted on substrate * All inputs and outputs are LVTTL compatible * Serial Presence Detect with E2PROM * Uses Infineon 256 Mbit SDRAM components in 32M x 8 organization and TSOPII-54 packages * Fully PC board layout compatible to INTEL's Rev. 1.0 module specification * Gold contact pad, card size: 133.35 mm x 31.75 mm x 4.00 mm (JEDEC MO-161-BA)
2 3 2
2 3 2
* SDRAM Performance: -7 PC133
fCK tAC
-7.5 PC133 133 5.4
-8 PC100 100 6
Unit MHz ns
Clock Frequency (max.) Clock Access time
133 5.4
Description The HYS 64V64220GU and HYS 72V64220GU are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organized as 64M x 64 and 64M x 72 in two banks high speed memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use "-7" speed sorted 256 Mbit Synchronous DRAMs (SDRAMs) to meet the PC133-222 requirements, "-7.5" for PC133-333 and "-8" components for PC100-222 applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL's module specification. The DIMMs have a serial presence detect, implemented with a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25" (31.75 mm) height.
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Ordering Information Type HYS 64V64220GU-7-D HYS 72V64220GU-7-D Code Package Descriptions Module Height 1.25" 1.25" 1.25" 1.25" 1.25" 1.25"
PC133-222-520 L-DIM-168-30 PC133 64M x 64 2 bank SDRAM module PC133-222-520 L-DIM-168-30 PC133 64M x 72 2 bank SDRAM module
HYS 64V64220GU-7.5-C2 PC133-333-520 L-DIM-168-30 PC133 64M x 64 2 bank HYS 64V64220GU-7.5-D SDRAM module HYS 72V64220GU-7.5-C2 PC133-333-520 L-DIM-168-30 PC133 64M x 72 2 bank SDRAM module HYS 72V64220GU-7.5-D HYS 64V64220GU-8-C2 HYS 72V64220GU-8-C2 PC100-222-620 L-DIM-168-30 PC100 64M x 64 2 bank SDRAM module PC100-222-620 L-DIM-168-30 PC100 64M x 72 2 bank SDRAM module
Note: All part numbers end with a place code, designating the die revision. Consult factory for current revision. Example: HYS 64V64220GU-8-C2, indicating Rev.C2 dies are used for SDRAM components.
ames in paranthese are for the x72 ECC versions; example: Pin 106 = (CB5)
Pin Definitions and Functions A0 - A12 BA0, BA1 CB0 - CB7 RAS CAS WE Address Inputs Bank Selects CLK0 - CLK3 CS0 - CS3 Clock Input Chip Select Power (+ 3.3 V) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection
DQMB0 - DQMB7 Data Mask
DQ0 - DQ63 Data Input/Output Row Address Strobe Column Address Strobe Read/Write Input
Check Bits (x72 organization only) VDD
VSS
SCL SDA N.C./DU
CKE0, CKE1 Clock Enable Address Format Part Number
Rows Columns 10
Bank Select 2
Refresh Period Interval 8k 64 ms 7.8 s
64M x 64/72 HYS64/72V64220GU 13
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Pin Configuration PIN# Symbol PIN# Symbol PIN# Symbol
VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 N.C. (CB4) N.C. (CB5) VSS N.C. N.C. VDD CAS DQMB4 DQMB5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 A12
PIN#
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Symbol
VSS CKE0 CS3 DQMB6 DQMB7 N.C. VDD N.C. N.C. CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 N.C. DU N.C. VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 N.C. SA0 SA1 SA2 VDD
1 VSS 43 VSS 85 2 DQ0 44 DU 86 87 3 DQ1 45 CS2 4 DQ2 46 DQMB2 88 5 DQ3 47 DQMB3 89 48 DU 90 6 VDD 91 7 DQ4 49 VDD 8 DQ5 50 N.C. 92 9 DQ6 51 N.C. 93 10 DQ7 52 N.C. (CB2) 94 11 DQ8 53 N.C. (CB3) 95 54 VSS 96 12 VSS 13 DQ9 55 DQ16 97 14 DQ10 56 DQ17 98 15 DQ11 57 DQ18 99 16 DQ12 58 DQ19 100 101 17 DQ13 59 VDD 18 VDD 60 DQ20 102 19 DQ14 61 N.C. 103 20 DQ15 62 DU 104 21 N.C. (CB0) 63 CKE1 105 106 22 N.C. (CB1) 64 VSS 23 VSS 65 DQ21 107 24 N.C. 66 DQ22 108 25 N.C. 67 DQ23 109 68 VSS 110 26 VDD 27 WE 69 DQ24 111 28 DQMB0 70 DQ25 112 29 DQMB1 71 DQ26 113 72 DQ27 114 30 CS0 115 31 DU 73 VDD 32 VSS 74 DQ28 116 33 A0 75 DQ29 117 34 A2 76 DQ30 118 35 A4 77 DQ31 119 120 36 A6 78 VSS 37 A8 79 CLK2 121 38 A10 80 N.C. 122 39 BA1 81 WP 123 82 SDA 124 40 VDD 83 SCL 125 41 VDD 126 42 CLK0 84 VDD Note: Pin names in parenthses are for the x72 ECC versions
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CS1 CS0 DQMB0 DQ(7:0) CS DQM DQ0-DQ7 D0 CS DQM DQ0-DQ7 D1 CS DQM DQ0-DQ7 D16 CS DQM DQ0-DQ7 D8 CS DQM DQ0-DQ7 D9 CS DQM DQ0-DQ7 D17 DQMB4 DQ(39:32) CS DQM DQ0-DQ7 D4 CS DQM DQ0-DQ7 D5 CS DQM DQ0-DQ7 D12 CS DQM DQ0-DQ7 D13
DQMB1 DQ(15:8)
DQMB5 DQ(47:40)
CB(7:0)
CS3 CS2 DQMB2 DQ(23:16) CS DQM DQ0-DQ7 D2 CS DQM DQ0-DQ7 D3 CS DQM DQ0-DQ7 D10 CS DQM DQ0-DQ7 D11 DQMB6 DQ(55:48) CS DQM DQ0-DQ7 D6 CS DQM DQ0-DQ7 D7
2
CS DQM DQ0-DQ7 D14 CS DQM DQ0-DQ7 D15
DQMB3 DQ(31:24)
DQMB7 DQ(63:56)
A0-A12, BA0, BA1 VDD C VSS RAS, CAS, WE CKE0 VDD
D0-D15, (D16, D17) D0-D15, (D16, D17) D0-D15, (D16, D17) D0-D15, (D16, D17) D0-D7, (D16)
E PROM (256 Word x 8 Bit) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP
47 k
Clock Wiring 32 M x 64 CLK0 CLK1 CLK2 CLK3 4 SDRAM + 4 SDRAM + 4 SDRAM + 4 SDRAM + 3.3 pF 3.3 pF 3.3 pF 3.3 pF 32 M x 72 5 SDRAM 5 SDRAM 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF
10 k
CKE1 D9-D15, (D17)
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 except otherwise noted.
BL012
Block Diagram: 64M x 64/72 Two Bank SDRAM DIMM Modules
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Absolute Maximum Ratings
Parameter Symbol min. Input / Output voltage relative to VSS Power supply voltage on VDD Storage temperature range Power dissipation per SDRAM component Data out current (short circuit) VIN, VOUT VDD T STG PD IOS - 1.0 - 1.0 -55 - - Limit Values max. 4.6 4.6 +150 1 50 V V
o
Unit
C
W mA
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V Parameter Input High Voltage Input Low Voltage Output High Voltage (I OUT = - 4.0 mA) Output Low Voltage (IOUT = 4.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output Leakage Current (DQ is disabled, 0 V < V OUT < V DD) Symbol min. Limit Values max. 2.0 - 0.5 2.4 - - 40 - 40 Unit V V V V
VIH VIL VOH VOL II(L) IO(L)
VDD + 0.3
0.8 - 0.4 40 40
A A
TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz
Parameter Symbol Limit Values max. 64M x 64 Input Capacitance
(A0 to A11, BA0, BA1, RAS, CAS, WE)
Capacitance
Unit
max. 64M x 72 144 40 43 72 25 17 8 8 pF pF pF pF pF pF pF pF 9.01
CI1 CI2 CICL CI3 CI4 CIO CSC CSD
5
105 32 40 65 20 17 8 8
Input Capacitance (CS0 - CS3) Input Capacitance (CLK0 - CLK3) Input Capacitance (CKE0, CKE1) Input Capacitance (DQMB0 - DQMB7) Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) Input Capacitance (SCL, SA0-2) Input/Output Capacitance INFINEON Technologies
HYS 64/72V64220GU SDRAM-Modules
Operating Currents per SDRAM Component TA = 0 to 70 oC, VDD = 3.3 V 0.3 V Parameter Operating current Test Condition - Symbol -7/ -7.5 -8 170 Unit Note mA
1, 2
max.
ICC1
230
tRC = tRC(MIN.), tCK = tCK(MIN.)
Outputs open, Burst Length = 4, CL = 3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access Precharge stand-by current in Power Down Mode CS = V IH(MIN.), CKE VIL(MAX.) Precharge Stand-by Current in Non-Power Down Mode CS = V IH (MIN.), CKE V IH(MIN.) No operating current CKE VIH(MIN.) I CC3N CKE VIL(MAX.) I CC3P 50 10 45 10 mA mA
1, 2 1, 2
tCK = min.
ICC2P
2
2
mA
1, 2
tCK = min.
ICC2N
40
30
mA
1, 2
tCK = min., CS = VIH(MIN.),
active state (max. 4 banks) Burst operating current tCK = min., Read command cycling Auto refresh current tCK = min., Auto Refresh command cycling Self refresh current Self Refresh Mode, CKE = 0.2 V Notes
-
ICC4
150
100
mA
1,2,3
-
ICC5
240
220
mA
1, 2
ICC6
3
3
mA
1
1. All values are shown per one SDRAM component. 2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation frequency for -7 & -7.5 and at 100 MHz for -8 modules. Input signals are changed once during tCK , excepts for I CC6 and for stand-by currents when tCK = infinity. 3. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 are assumed and the data out current is excluded.
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AC Characteristics 1), 2) TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns Parameter
Symbol
Limit Values -7 -7.5 PC133-222 PC133-333 -8 PC100-222
Unit Note
min. max min. max. min. max. Clock Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System Frequency CAS Latency = 3 CAS Latency = 2 Clock Access Time CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Setup and Hold Times Input Setup Time Input Hold Time Power Down Mode Entry Time Power Down Mode Exit Setup Time Mode Register Setup Time Transition Time (rise and fall) Common Parameters RAS to CAS Delay Precharge Time Active Command Period Cycle Time Bank to Bank Delay Time
tCK
7.5 7.5 - - 133 133 5.4 5.4 - - 7.5 10 - - - - 2.5 2.5 - - 133 100 5.4 6 - - 10 10 - - - - 3 3 - - 100 100 6 6 - - ns ns
-
fCK
- - MHz MHz
-
tAC
- - ns ns ns ns
3), 4)
tCH tCL
2.5 2.5
4) 4)
tCS tCH tSB tPDE tRSC tT
1.5 0.8 - 1 2 1
- - 1 - - -
1.5 0.8 - 1 2 1
- - 1 - - -
2 1 - 1 2 1
- - 1 - - -
ns ns CLK CLK CLK ns
5) 5) 6) 7)
-
tRCD tRP tRAS tRC tRRD
15 15 42 60 14 1
- - - - - -
20 20 45 67.5 15 1
- - - - -
20 20 70 16 1
- - - - -
ns ns ns ns
- - - - -
100k 50
100k ns
CAS to CAS Delay Time (same bank) tCCD
CLK -
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AC Characteristics (cont'd) 1), 2)
TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values -7 -7.5 PC133-222 PC133-333 -8 PC100-222
Unit Note
min. max min. max. min. max. Refresh Cycle Refresh Period (8192 cycles) Self Refresh Exit Time Read Cycle Data Out Hold Time Data Out to Low Impedance Data Out to High Impedance DQM Data Out Disable Latency Write Cycle Data Input to Precharge (write recovery) DQM Write Mask Latency
tREF tSREX
64 -
- 1
- 1
64 -
- 1
64 -
ms CLK
6) 8)
tOH tLZ tHZ tDQZ
3 0 3 -
- - 7 2
3 0 3 -
- - 7 2
3 0 3 -
- - 8 2
ns ns ns
2)
-
9)
CLK -
tWR tDQW
2 0
- -
2 0
- -
2 0
- -
CLK - CLK -
Notes 4. All AC characteristics are shown on SDRAM component level. An initial pause of 100 s is required after power-up, then a Precharge All Banks command must be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation can begin. 5. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V IH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V. 6. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns must be added to this parameter. 7. Rated at 1.4 V 8. If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 9. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to "wake-up" the device. 10.Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal is assumed latched on the next cycle.
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11.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 12.This is referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
t CH CLOCK 1.4 V t CL t IH tT 2.4 V 0.4 V
t IS
INPUT tAC t LZ OUTPUT
1.4 V tAC t OH 1.4 V t HZ
IO.vsd
I/O 50 pF
Measurement conditions for tAC and tOH
Serial Presence Detect A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus).
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SPD-Table for 64M x 64 (512 MByte non-ECC) Modules HYS64V64220GU Byte Description # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL = 3 Access Time from Clock at CL = 3 DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-toBack Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time at CL = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay t RCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) SDRAM Input Setup Time SDRAM Input Hold Time SPD Entry Value -7 128 256 SDRAM 13 10 2 64 0 LVTTL 7.5 / 10 ns 5.4 / 6 ns non-ECC Self-Refresh, 7.8 s x8 na tCCD = 1 CLK 1, 2, 4 & 8 4 CL = 2 & 3 CS latency = 0 Write latency = 0 unbuffered VDD tol +/- 10% 7.5 / 10.0 ns 5.4 / 6.0 ns not supported not supported 15 / 20 ns 14 / 15 / 16 ns 15 / 20 ns 42 / 45 / 50 ns 256 MByte 1.5 / 2.0 ns 0.8 / 1.0 ns Hex 64M x 64 -7.5 80 08 04 0D 0A 02 40 00 01 75 54 00 82 08 00 01 0F 04 06 01 01 00 0E A0 60 FF FF 14 0F 14 2D 40 15 08
-8
75 54
A0 60
75 54 00 00 0F 0E 0F 2A 15 08
A0 60 FF FF 14 10 14 32 20 10
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SPD-Table for 64M x 64 (512 MByte non-ECC) Modules HYS64V64220GU Byte Description # 34 35 36-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99125 126 127 128+ SDRAM Data Input Hold Time SDRAM Data Input Setup Time Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Locaction Module Part Number Module Revision Code Module Manufacturing Code Module Serial Number Superset Information Frequency Specification 100 MHz Support Details Unused Storage Locations SPD Entry Value -7 15 08 FF 12 F4 Hex 64M x 64 -7.5 15 08 FF 12 37 C1 INFINEO(N)
1.5 / 2.0 ns 0.8 / 1.0 ns - Revision 1.2 - -
-8 20 10 FF 12 9A
- -
64 FF FF
64 FF FF
64 FF FF
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SPD-Table for 64M x 72 (512 MByte ECC) Modules HYS72V64220GU Byte# Description SPD Entry Value -7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL = 3 Access Time from Clock at CL = 3 DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-toBack Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time at CL = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) SDRAM Input Setup Time SDRAM Input Hold Time 128 256 SDRAM 13 10 2 72 0 LVTTL 7.5 / 10 ns 5.4 / 6 ns ECC Self-Refresh, 7.8 s x8 x8 tCCD = 1 CLK 1, 2, 4 & 8 4 CL = 2 & 3 CS latency = 0 Write latency = 0 unbuffered VDD tol +/- 10% 7.5 / 10.0 ns 5.4 / 6.0 ns not supported not supported 15 / 20 ns 14 / 15 / 16 ns 15 / 20 ns 42 / 45 / 50 ns 256 MByte 1.5 / 2.0 ns 0.8 / 1.0 ns Hex 64M x 72 -7.5 80 08 04 0D 0A 02 48 00 01 75 54 02 82 08 08 01 0F 04 06 01 01 00 0E A0 60 FF FF 14 0F 14 2D 40 15 08
-8
75 54
A0 60
75 54 00 00 0F 0E 0F 2A 15 08
A0 60 FF FF 14 10 14 32 20 10
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SPD-Table for 64M x 72 (512 MByte ECC) Modules HYS72V64220GU Byte# Description SPD Entry Value -7 15 08 FF 12 06 Hex 64M x 72 -7.5 15 08 FF 12 49 C1 INFINEO(N)
34 35 36-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99-125 126 127 128+
SDRAM Data Input Hold Time SDRAM Data Input Setup Time Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Locaction Module Part Number Module Revision Code Module Manufacturing Code Module Serial Number Superset Information Frequency Specification 100 MHz Support Details Unused Storage Locations
1.5 / 2.0 ns 0.8 / 1.0 ns - Revision 1.2 - -
-8 20 10 FF 12 AC
- -
64 FF FF
64 FF FF
64 FF FF
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Package Outlines L-DIM-168-30 (JEDEC MO-161-BA) SDRAM DIMM Module Package HYS 64/72V64220GU
133.35 + 0.15
127.35
31.75 + 0.13
4 max.
4
*)
3 1 3 1.27 10 11 6.35 42.18 91 x 1.27 = 115.57 3.125 40 41 6.35 84
1.27 + 0.1
85
94
2 95
124
125
168
17.78
*)
3 min.
3
Detail of Contacts
*) on ECC modules only
0.25
1 1.27
L-DIM-168-30
2.55
Note: All tolerances according to JEDEC standard
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Change List:
14.1.1999 18.4.1999
12.5.99 3.8.99 23.8.99 6.9.99 20.10.99 2.12.99 20.1.2000 10.3.2000
10.5.2000 5.03.2001
24.07.2001 06.09.2001
Input capacitances adjusted -8A speed sort added Infineon logo added SPD codes updated according to new 256M speedsorts Some ICC current values changed due to new inputs PC133 merged into this datasheet Byte 126 changed to 64h for PC133 modules Template from R&L CL=2 max. frequency changed to 83 Mhz for -7.5 modules Some timing parameters adjusted according to INTELs PC133 specification Capacitance values for x72 adjusted (new measurements) Implemented differences between 256Mbit S20 and S17 PC133 modules 256Mbit S20 based PC133 modules are backward compatible to PC100 3-2-2 256Mbit S17 based modules are backwards compatible to PC100-2-2-2 leading to changes in SPD code of bytes 23, 63 (checksum) and 126 TPCR issued Reference to JEDEC MO-161-BA added -8A and -8B speed sorts removed PC133 timing parameters only for 256M S17 and later versions References to 256M S20 removed ICC currents according to 256M S17 datasheet 256M S14 based modules addded -7 speed sort added for 256M S14 modules SCR : Absolute Maximum Ratings table added
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